1. Field of the Invention
This invention relates to planarization of surfaces exhibiting a grain boundary and, more specifically, to planarization of electrode surfaces in integrated circuits electrodes.
2. Brief Description of the Prior Art
As the size of components in integrated circuits decreases, new problems continually occur which were not encountered with larger dimension components. In the case of the next generations of dynamic random access memories (DRAMs) which are now under development, capacitors are required having dielectric layers as thin as 40 .ANG. and possibly even less equivalent oxide thickness. If reoxided nitride (a deposited thin nitride followed by oxidation of this nitride) thin dielectric films are used, the physical thickness will be from about 40 to about 60 .ANG..
Polycrystalline materials, such as polysilicon and polycrystalline metals, which are generally used as capacitor electrodes in integrated circuits, generally exhibit grain boundary. Such materials exhibit surface voids and surface irregularities at the grain boundaries. The term "voids" as used herein is defined to include voids in its standard usage as well as a physical or lattice mismatch (i.e., the boundary between two grains with a different lattice orientation). At thicknesses in the range as low as about 40 .ANG., the sensitivity of the dielectric strength to the surface roughness of the electrode will be high. When polycrystalline materials are used as electrodes in conjunction with such thin dielectric layers, such as, for example, in the fabrication of capacitors in integrated circuits, the integrity and dielectric strength of the fabricated capacitors degrade to some extent, depending upon the thickness of the dielectric layers and the surface roughness of the polycrystalline electrodes. Ultrathin dielectric films, such as, for example, nitride films as thin as 40 to 60 .ANG. show obvious degradation in dielectric properties such as leakage, gate oxide integrity or breakdown (GOI), time dependent dielectric breakdown (TDDB) and defect density when deposited on polysilicon compared to deposition thereof on single crystal silicon substrates.
It has been suggested to use amorphous silicon in place of the polycrystalline silicon to avoid the problems caused by the grain boundaries. The problem with this approach is that the amorphous silicon becomes polycrystalline when exposed to the temperatures experienced during semiconductor fabrication.